1. Field of the Invention
The present invention relates to a semiconductor memory device. Particularly, the present invention relates to a clock control signal and output enable signal generator of semiconductor memory device in which a signal generating channel for controlling a low impedance of an output signal is different from that for controlling a high impedance, thereby improving an output enable signal generating speed, and at the same time supporting double cycle deselect, single cycle deselect and write pass through functions, both in a flow through operation and a pipe line read mode.
2. Description of the Prior Art
In a clock control signal and output enable signal generator of a conventional semiconductor memory device, an output enable signal shift is delayed. That is because a signal generating channel for controlling a low impedance in an output signal is identical to that for controlling a high impedance. Therefore, there has been a problem in that, when an output signal of the semiconductor memory device is shifted from a low impedance to a high impedance and from a high impedance to a low impedance, the shift speed is delayed.
This problem has been addressed by making the signal generating channel for controlling a low impedance different from the signal generating channel for controlling a high impedance. But a pipelined read operation of the semiconductor memory device includes single cycle deselect, double cycle deselect and write pass through functions. A problem is that all the single cycle deselect, double cycle deselect and write pass through functions cannot be supported (backed-up) with such different channels.